For decades, chips improved by making transistors smaller. A transistor is a switch, and its job is to let current flow when a voltage is applied to its gate and block it otherwise. As dimensions shrank, that job got harder, because the gate has less control over a very small channel, and current leaks through even when the switch is meant to be off. Engineers answered by changing the geometry. Early planar transistors gave way to fin-shaped transistors, in which the gate covers the channel on three sides. Nanowire transistors take the idea to its conclusion by surrounding the channel completely, which gives the gate the strongest possible grip on the current. The approach is known as gate-all-around, and it is now entering production.
How does a nanowire transistor operate?
In a nanowire transistor the channel is a thin wire of semiconductor, typically silicon, only a few nanometres across, with source and drain regions at either end. The gate material wraps around the wire like a sleeve, separated from it by a thin insulating layer. When voltage is applied to the gate, the electric field reaches the channel from every side, so it can switch the whole cross-section on and off cleanly. This improves electrostatic control, which reduces leakage and allows the transistor to switch with a smaller voltage. Variations use flat sheets rather than round wires. These nanosheet devices offer more conducting area for a given footprint, and they have become a leading commercial implementation of gate-all-around technology.
How does integration change the chip?
Because the channels are thin, several can be stacked vertically within one transistor, with the gate material filling the spaces between them. Stacking raises the current a transistor can deliver without enlarging its footprint on the chip, and the designer can tune the width of the sheets to favour speed or low power. Cell layouts, the standard building blocks of logic, are redrawn to take advantage of the new geometry, and wiring and power delivery must be adapted to feed denser circuits. Nanowires are also studied as building blocks for sensors, where their very large surface area compared with their volume makes them sensitive to chemical and biological signals, and for novel devices that combine different materials in a single wire.
Where do the efficiency benefits come from?
Better electrostatic control has two consequences for energy. Less current leaks when the transistor is off, which cuts the standby power that dominates in idle circuits. And because the gate controls the channel so tightly, the transistor can operate at lower voltage while still switching sharply, which lowers the energy consumed with every operation, since dynamic power depends strongly on voltage. These gains are the reason that gate-all-around designs are attractive for both mobile devices and data centres. The benefits are real, though they come with the usual compromises, and designers weigh them against cost, speed and the difficulty of manufacture at each new generation of chips.
Manufacturing challenges and why it matters
Building stacked nanowires is difficult. Fabrication usually grows alternating layers of silicon and a sacrificial material, patterns them into fins, and then selectively etches away the sacrificial layers to leave suspended channels, which must then be coated uniformly with insulator and gate metal in extremely narrow gaps. Variations of a fraction of a nanometre change the transistor's behaviour, so uniformity is critical. Contacts and parasitic resistance become significant as dimensions fall, and heat is harder to remove from densely packed devices. These challenges explain why progress is incremental. Nanowire and nanosheet transistors matter because they offer a route to keep improving performance and efficiency when conventional scaling runs out of room.
When a transistor gets small enough, the geometry of the gate matters more than the size of the gate.
